Lam Research commands approximately 50% of the global conductor etch market, making it the undisputed leader in the most process-intensive step of semiconductor manufacturing. Etch is the foundation of Lam's business, generating roughly half of total revenue (~$10.3B in CY2025). Every advanced semiconductor structure -- 3D NAND layers, HBM through-silicon vias, gate-all-around transistors, and advanced packaging interconnects -- requires progressively more etch steps as device complexity increases. CY2025 revenue grew 30%+ for etch, driven by NAND recovery (24% of systems revenue, up from 11%), HBM buildout (only 7% of DRAM bits are HBM), and advanced packaging exceeding $1B. The key debate is whether etch intensity gains are structural (rising with each technology node) or cyclical (driven by temporary memory investment surges).
Lam Research holds approximately 50% share of the global conductor etch market, making it the dominant player in this critical semiconductor manufacturing step
HBM (High Bandwidth Memory) stacking requires through-silicon via (TSV) etching to interconnect vertically stacked DRAM dies. Each HBM generation increases layer count: HBM3 uses 8-12 layers, HBM3E uses 8-12 layers with improved performance, and HBM4 will move to 16-layer stacking. Each additional layer requires more TSV etch steps, making Lam's etch tools increasingly critical. Management described HBM as 'definitely the hot thing in DRAM.' With only 7% of DRAM bits being HBM in 2025, the growth runway extends for multiple years. HBM4/4e with 16-layer stacking represents a step-function increase in etch content per die.
HBM4 will move to 16-layer die stacking, up from 8-12 layers in HBM3/3E, roughly doubling the TSV etch steps required per stack
3D NAND requires the deepest high-aspect-ratio etch in semiconductor manufacturing -- etching channels through 200+ layers of alternating oxide/nitride films. Each technology generation adds more layers: the industry is transitioning from 128-layer to 256-layer NAND, which roughly doubles the etch depth and process complexity. NAND reached 24% of Lam's systems revenue (up from 11% in the prior quarter), with record upgrade revenue up 90%+ YoY as fabs convert to higher layer counts. The NAND recovery is the strongest single driver of Lam's etch revenue growth, but NAND capex is historically the most volatile segment in WFE.
NAND reached 24% of Lam's systems revenue, up from 11% in the prior quarter, with record upgrade revenue up 90%+ YoY
The transition from FinFET to gate-all-around (GAA) transistors at sub-3nm nodes creates new etch requirements. GAA requires selective etching of nanosheet stacks with atomic-level precision, including selective removal of sacrificial SiGe layers while preserving Si channels. This is fundamentally more complex than FinFET etching and increases etch steps per wafer by an estimated 20-30%. TSMC's N2 and Samsung's 3nm GAA are both in production, with Intel's 18A also adopting GAA. As the leading logic foundries transition, Lam's conductor etch tools see increased content per wafer pass.
GAA transistor transition increases etch steps per wafer by an estimated 20-30% compared to FinFET, due to the complexity of selective nanosheet etching